The clock generator in a motherboard is often changed by computer enthusiasts to control the speed of their cpu fsb gpu and ram.
Programmable clock generator chip.
Development and programming kit for easy pll design and programming ti pro clock open in new find other clock generators description.
This is idts fifth generation of programmable clock technology versaclock 5.
Waveform generation is required in various types of sensing actuation and time domain reflectometry tdr applications.
A programmable circuit for generating a clock signal is disclosed.
Description the 5p49v5914 is a programmable clock generator intended for high performance consumer networking industrial computing and data communications applications.
No external components ar.
Description the 5p49v5907 is a programmable clock generator intended for high performance consumer networking industrial computing and data communications applications.
The cdce949 and cdcel949 are modular pll based low cost high performance programmable clock synthesizers multipliers and dividers.
The output frequency and phase are software programmable allowing easy tuning.
These devices are the industry s first single chip programmable clock generators capable of generating eight different output frequencies with less than 300 femtoseconds rms phase jitter over the standard 12 khz to 20 mhz integration range.
Programmable clock generators allow the number used in the divider or multiplier to be changed allowing any of a wide variety of output frequencies to be selected without modifying the hardware.
The 5p49v5907 is a programmable clock generator intended for high performance consumer networking industrial computing and data communications applications.
Configurations may be stored in on chip one time programmable otp memory or changed using i2c interface.
They generate up to 9 output clocks from a single input frequency.
The ad9833 is a low power programmable waveform generator capable of producing sine triangular and square wave outputs.
The heart of the chip its programmable clock core consists of a pll with programmable drive and programmable load.